The output is initially 4.5V for logic 1 and 1.5V for logic 0 ... From there, with some size reductions, a Master-Slave J-K Flip Flop, similarly using NAND gates and inverters, can be built.

I used T flip flops here, but really they could represent any kind of logic no matter how complex. The key is we expect the same output from them. In fact, there’s no reason each one has to get ...

From the transition table of Table 8.6 we add Columns (1), (2), and (3) to the characteristic table of the JK flip flop as shown in Table 8.7. Table 8.7: Characteristic table for ...